Memory devices, such as a NAND or a NOR flash memory devices, dynamic random access memory devices (DRAMs), static random access memory device (SRAMs), or the like, are generally fabricated on semiconductor wafers. Each of these wafers typically contains a number of individual integrated circuit memory devices formed in rectangular areas known as dies. After fabrication, each die is separated, or diced, then packaged in a format suitable for the end user.
Before or after dicing and packaging, a manufacturer may test its integrated circuit devices as part of a quality program to improve end-use reliability. Such tests are generally performed on highly-specialized testing systems or tester hardware. Prior to dicing, tests may be performed by the testing system on each die of a semiconductor wafer in pattern. The tester hardware may test each die individually or it may test multiple dies concurrently. Subsequent to dicing, tests may be performed by the testing system on multiple packaged components in pattern. The tester hardware may test each component individually or it may test multiple components concurrently.
Testing is usually performed by placing the memory device in a test mode that is different from the normal operating mode. Test modes often enable one or more registers to be accessed that are not accessible during normal operation. A high voltage is often applied to a memory device to place the memory device into a test mode. This voltage is typically greater than the normal operating voltage, e.g., approximately 50 to 100 percent greater than the normal operating voltage, supplied to the memory device. The memory device is configured to enter the test mode in response to receiving the high voltage signal.
High voltages are often used for accessing a test mode to prevent unauthorized personnel, such as intermediate and end users, from accessing the test mode, because many unauthorized personnel do not have such high voltages available to the memory device as installed. Moreover, using high voltages for accessing a test mode prevents memory devices from being inadvertently placed in the test mode during normal operation. However, for some applications, it may be desirable to place the memory device into test mode when there are no high voltages available. Therefore, low-voltage access methods have been proposed. However, low-voltage access methods can make it easier for hackers to hack in to the test mode registers and to alter the intended operation of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives for accessing test modes of memory devices.